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Software in the Loop Simulation for Embedded Software Test


The workload and cost of validating software systems embedded in a technical environment (embedded software) often account for as much as 50% of the total development budget.  Improving the process for testing the software of embedded systems, therefore, not only permits high potential savings in terms of  development costs, it also enhances product quality.SiLEST is co-funded by the German Federal Ministry of
Education and Research (BMBF, http://www.bmbf.de) as part of the “Software Engineering 2006” research initiative.


aimPart of the SiLEST (Software in the Loop for Embedded Software Test) joint project looks at the potential of testing the software of embedded systems within a simulated environment. Attention focuses on identifying the possible applications and limits of the software-in-the-loop (SiL) test method with the aim of conducting “in the loop” simulation at an early stage on a cost-effective, reproducible, retraceable and automatic basis. This process is also compared with the established hardware-inthe-loop (HiL) test method in order to reveal and contrast the benefits and  drawbacks associated with both methods.



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Prof. Dr.-Ing. Clemens Gühmann
+49 30 314-29393
Building EN
Room EN539


Uzmee Bazarsuren
+49 30 39978-9374

Dr.-Ing. Thomas Liebezeit